in a way that leads to a cost-effective, high-performance computer system. The system, however, is
no better than the components from which it is built.
The basic building block of the network is the switch (router) chip that interconnects the
processing nodes according to some prescribed topology .The topology and how the system is packaged
are closely related; typical packaging schemes are hierarchical - chips are packaged onto printed
circuit boards, which in turn are packaged into an enclosure (e.g., rack), which are connected together
to create a single system.
Figure 2.1: Off-chip bandwidth of prior routers, and ITRS predicted growth.
The past 20 years has seen several orders of magnitude increase in off-chip bandwidth spanning
from several gigabits per second up to several terabits per second today. The bandwidth shown in
Figure 2.1 plots the total pin bandwidth of a router - i.e., equivalent to the total number of signals
times the signaling rate of each signal - and illustrates an exponential increase in pin bandwidth.
Moreover, we expect this trend to continue into the next decade as shown by the International
Roadmap for Semiconductors (ITRS) in Figure 2.1 , with 1000s of pins per package and more than
100 Tb/s of off-chip bandwidth. Despite this exponential growth, pin and wire density simply does
not match the growth rates of transistors as predicted by Moore's Law.