Figure 6.1: Baseline virtual channel router.
RC VA SA ST
Head flit Body flit
Figure 6.2: (a) Packets are broken into one or more flits (b) Example pipeline of flits through the baseline
These steps are repeated for each flit of the packet and upon the transmission of the tail flit ,
the final flit of a packet, the virtual channel is freed and is available for another packet. A simple
pipeline diagram of this process is shown in Figure 6.2 (b) for a three-flit packet assuming each step
takes a single cycle.
SCALING BASELINE MICROARCHITECTURE TO HIGH
As radix is increased, a centralized approach to allocation rapidly becomes infeasible because the
wiring, die area, and the latency all increase to prohibitive levels. In this section, we introduce