Networking Reference
In-Depth Information
VC
Allocator
Routing
computation
Router
Switch
Allocator
VC 1
VC 2
Input 1
Output 1
VC v
VC 1
VC 2
Input k
Output k
VC v
Crossbar switch
Figure 6.1: Baseline virtual channel router.
1
2
3
4
5
6
Cycle
Packet
RC VA SA ST
Head Flit
SA ST
Body Flit
Head flit Body flit
Tail flit
Tail Flit
SA ST
(a)
(b)
Figure 6.2: (a) Packets are broken into one or more flits (b) Example pipeline of flits through the baseline
router.
These steps are repeated for each flit of the packet and upon the transmission of the tail flit ,
the final flit of a packet, the virtual channel is freed and is available for another packet. A simple
pipeline diagram of this process is shown in Figure 6.2 (b) for a three-flit packet assuming each step
takes a single cycle.
6.2
SCALING BASELINE MICROARCHITECTURE TO HIGH
RADIX
As radix is increased, a centralized approach to allocation rapidly becomes infeasible because the
wiring, die area, and the latency all increase to prohibitive levels. In this section, we introduce
 
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