Networking Reference
In-Depth Information
6. SCALABLE SWITCH MICROARCHITECTURE
plesiochronously at data rates of 2.5Gb/s, 5Gb/s, and 10Gb/s. The width of the links can vary from
1
×
or 4
for a total link bandwidth of 10Gb/s (SDR), 20Gb/s (DDR) or 40Gb/s (QDR).
The microarchitecture of the IS4 takes a more conventional approach with a non-blocking
×
×
×
12
to produce
a 36-port router. Each host in the Infiniband fabric is labeled with a local identifier (LID) 1 Each
crossbar uses a 48K entry linear forwarding table (LFT) to route unicast packets by indexing into
the LFT using the destination LID.
12 crossbar as the basic building block (Figure 6.9 ). The crossbars are replicated 3
(a) Packaged IS4 switch chip.
×
(b) Block diagram of the IS4 switch chip with 36 ports each 4
10 Gb/s, for an aggregate of 2.88
Tb/s off-chip bandwidth
Figure 6.9: Packaged silicon and block diagram of the Mellanox InfiniScale IV router.
1 A LID is essentially the host endpoint or node identifier.
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